68kMLA Classic Interface

Hi, demik. The most useful card for reference outside the OEM part would be a G3 accelerator for the 6100. You can get all your measurements from any one of those boards very easily, especially the offset required for connector<->backplane fit. I can haul down the 6100 and scan the solder side of the G3 for starters.

I'll be following your progress very closely because I suddenly now have one more to add to the pair of risers on the backburner already.  :🙂 Your observation about the personality card connector had me confirm that a Left Angle Adapter to flop over the Whisper card in my long procrastinated Beige G3 2U Rackmount build works nicely. I'd planned on bodging a pair of PCI riser cables to make that connection, but now I'm inspired! That connector info is much welcomed, trag, THX! The other riser project's a pair of offset, lowrider "second slot" PCI adapters, one for the TAM and the other for the drawer of the 6360 and its single slot AIO variations.

Have you found a rapid prototyping fab that can do edge card connectors of proper thicknesses yet? That was where procrastination set in for me almost three years ago. Anybody got info on sources? ISTR the ROM and SIMM edgecard thicknesses being a bit of a hurdle?

Old SIMM, e.g. 30 pin, 64 pin, are .050" or 1.27 mm.   1.2mm is a little too thin.   More modern stuff is .063" or 1.6mm and everything is more politely standardized at that thickness.

View attachment 33185

This should be a lot better. Just scale the 4 inches between 1"& 5" to life size in something like Illustrator. You can then create boxes from point to point to read off all your measurements/offsets etc. The other way to go about it is to work from the grid spacing of the edge card slot's soldertails. PCB dimensions are a red herring, connector grids are hard numbers. I'll see if I can come up with the Sonnet Card for a sharper image.

I threw the DOS riser in for shiggles and gits. Do you need another scan of that one too?

Table 4-9 VRAM SIMM pin assignments

Pin | Name   | Pin | Name   | Pin | Name
----+--------+-----+--------+-----+--------
1   | +5 V   | 24  | DQ4    | 47  | DQ10
2   | DSF*   | 25  | DQ5    | 48  | A6
3   | SDQ0   | 26  | SDQ7   | 49  | A7
4   | SDQ1   | 27  | SDQ6   | 50  | A8
5   | /DTOE0†| 28  | NC     | 51  | NC
6   | DQ0    | 29  | +5 V   | 52  | +5 V
7   | DQ1    | 30  | DQ7    | 53  | GND
8   | SDQ3   | 31  | DQ6    | 54  | GND
9   | SDQ1   | 32  | /CAS0  | 55  | SDQ12
10  | /WE0   | 33  | A4     | 56  | SDQ13
11  | /RAS   | 34  | A5     | 57  | NC
12  | /SE0   | 35  | GND    | 58  | DQ12
13  | DQ3    | 36  | SC     | 59  | DQ13
14  | DQ2    | 37  | SCQ8   | 60  | SDQ15
15  | A0     | 38  | SDQ9   | 61  | SDQ14
16  | A1     | 39  | /DTOE1 | 62  | NC
17  | A2     | 40  | DQ8    | 63  | NC
18  | A3     | 41  | DQ9    | 64  | DQ15
19  | GND    | 42  | SDQ11  | 65  | DQ14
20  | GND    | 43  | SDQ10  | 66  | /CAS1
21  | SDQ4   | 44  | /WE1   | 67  | +5 V
22  | SDQ5   | 45  | /SE1   | 68  | +5 V
23  | NC     | 46  | DQ11

* The DSF pin must be tied to either +5 V or ground.
† A slash before a signal name indicates that it is in the low state when active.

Here what's being done :

- Created a KiKad library for Apple Connectors 

- Diagram done 

- PCB Layout and routing done 

- Bough enough component for a first batch of risers (using connector EDAC 302-182-520-900) 

You're going about this in a beautifully organised fashion.  Are you planning to release the KiCad library for wider consumption?

Turns out Wakefield-Vette still makes PowerPC specific heatsinks, and one where the clip fits, although instead of the X-pattern, it's two parallel clips.
From Mouser, or from DigiKey.